COP840CJ Datasheet, PDF (20/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

Modulator/Timer (Continued)
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FIGURE 12. Mode 2a: 50% Duty Cycle Output
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FIGURE 13. Mode 2b: Variable Duty Cycle Output
Comparator
The device has one differential comparator. Ports L0–L2 are
used for the comparator. The output of the comparator is
brought out to a pin. Port L has the following assignments:
L0 Comparator output
L1 Comparator negative input
CMPOE Enables comparator output to pin L0 (“1”= en-
able), CMPEN bit must be set to enable this func-
tion. If CMPEN = 0, L0 will be 0.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power the program
should also disable the comparator before the device enters
the HALT mode.
L2 Comparator positive input
THE COMPARATOR STATUS/CONTROL BITS
These bits reside in the CNTRL2 Register (Address 0CC)
CMPEN Enables comparator (“1” = enable)
CMPRD Reads comparator output internally (CMPEN = 1,
CMPOE = X)
The user program must set up L0, L1, and L2 ports correctly
for comparator Inputs/Output. L1 and L2 need to be config-
ured as inputs and L0 as output. Table 8 shows the DC and
AC characteristics for the comparator.
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