COP840CJ Datasheet, PDF (11/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

Pin Descriptions
V_CC and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
RESET is the master reset input. See Reset description.
PORT I is a 4-bit Hi-Z input port.
PORT L is an 8-bit I/O port.
There are two registers associated with the L port: a data
register and a configuration register. Therefore, each L I/O
bit can be individually configured under software control as
shown below:
Port L
PORT L
Port L
Config.
Data
Setup
0
0
Hi-Z input (TRI-STATE)
0
1
Input with weak pull-up
1
0
Push-pull zero output
1
1
Push-pull one output
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration register
[00D1] and the input pins [00D2].
Port L has the following alternate features:
L0 MIWU or CMPOUT
L1 MIWU or CMPIN−
L2 MIWU or CMPIN+
L3 MIWU
L4 MIWU (high sink current capability)
L5 MIWU (high sink current capability)
L6 MIWU (high sink current capability)
L7 MIWU or MODOUT (high sink current capability)
The selection of alternate Port L functions is done through
registers WKEN [00C9] to enable MIWU, and CNTRL2
[00CC] to enable comparator and modulator.
All eight L-pins have Schmitt Triggers on their inputs.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7).
All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore each G port
bit can be individually configured under software control as
shown below:
Port G
Port G
PORT G
Config.
Data
Setup
0
0
Hi-Z input (TRI-STATE)
0
1
Input with weak pull-up
1
0
Push-pull zero output
1
1
Push-pull one output
Three data memory address locations are allocated for this
port, one for data register [00D4], one for configuration reg-
ister [00D5] and one for the input pins [00D6]. Since G6 and
G7 are Hi-Z input only pins, any attempt by the user to con-
figure them as outputs by writing a one to the configuration
register will be disregarded. Reading the G6 and G7 configu-
ration bits will return zeros. Note that the device will be
placed in the Halt mode by writing a “1” to the G7 data bit.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock
option is R/C- or external clock)
Pins G1 and G2 currently do not have any alternate func-
tions.
The selection of alternate Port G functions is done through
registers PSW [00EF] to enable external interrupt, and
CNTRL1 [00EE] to select TIO and MICROWIRE operations.
PORT D is a four bit output port that is preset high when
RESET goes low. One data memory address location is allo-
cated for the data register [00DC].
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay
above 0.8 V_CC to prevent the chip from entering special modes. Also
keep the external loading on D2 to < 1000 pF.
Functional Description
The internal architecture is shown in the block diagram. Data
paths are illustrated in simplified form to depict how the vari-
ous logic elements communicate with each other in imple-
menting the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or shift
operations in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PC is the 15-bit Program Counter register. PU is the upper
7 bits of the program counter (PC). PL is the lower 8 bits
of the program counter (PC).
B is the 8-bit address register and can be auto incre-
mented or decremented.
X is the 8-bit alternate address register and can be auto
incremented or decremented.
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM).
B, X and SP registers are mapped into the on-chip RAM. The
B and X registers are used to address the on-chip RAM. The
SP register is used to address the stack in RAM during sub-
routine calls and returns. The SP must be initialized by soft-
ware before any subroutine call or interrupts occur.
MEMORY
The memory is separated into two memory spaces: program
and data.
PROGRAM MEMORY
Program memory consists of 2048 x 8 ROM. These bytes of
ROM may hold instructions or constant data. The memory is
addressed by the 15-bit program counter (PC). ROM can be
indirectly read by the LAID instruction for table lookup.
DATA MEMORY
The data memory address space includes on-chip RAM, I/O
and registers. Data memory is addressed directly by instruc-
tions or indirectly through the B, X and SP registers. The de-
vice has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers”, these can be loaded immediately,
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