COP840CJ Datasheet, PDF (18/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

WATCHDOG (Continued)
DS012851-21
FIGURE 10. WATCHDOG Timer Block Diagram
Modulator/Timer
The MODULATOR/TIMER contains an 8-bit counter and an
8-bit autoreload register (MODRL address 0CF Hex). The
Modulator/Timer has two modes of operation, selected by
the control bit MC3. The Modulator/Timer Control bits MC1,
MC2 and MC3 reside in CNTRL2 Register.
MODE 1: MODULATOR
The Modulator is used to generate high frequency pulses on
the modulator output pin (L7). The L7 pin should be config-
ured as an output. The number of pulses is determined by
the 8-bit down counter. Under software control the modulator
input clock can be either CKI or t_C. The t_C clock is derived by
dividing down the oscillator clock by a factor of 10. Three
control bits (MC1, MC2, and MC3) are used for the
Modulator/Timer output control. When MC2 = 1 and MC3 =
1, CKI is used as the modulator input clock. When MC2 = 0,
and MC3 = 1, t_Cis used as the modulator input clock. The
user loads the counter with the desired number of counts
(256 max) and sets MC1 to start the counter. The modulator
autoreload register is loaded with n-1 to get n pulses. CKI or
t_C pulses are routed to the modulator output (L7) until the
counter underflows (Figure 11). Upon underflow the hard-
ware resets MC1 and stops the counter. The L7 pin goes low
and stays low until the counter is restarted by the user pro-
gram. The user program has the responsibility to time-out
the low time. Unless the number of counts is changed, the
user program does not have to load the counter each time
the counter is started. The counter can simply be started by
setting the MC1 bit. Setting MC1 by software will load the
counter with the value of the autoreload register. The soft-
ware can reset MC1 to stop the counter.
MODE 2: PWM TIMER
The counter can also be used as a PWM Timer. In this mode,
an 8-bit register is used to serve as an autoreload register
(MODRL).
1. 50% Duty Cycle:
When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle
free running signal is generated on the L7 output pin
(Figure 12). The L7 pin must be configured as an output
pin. In this mode the 8-bit counter is clocked by t_C. Set-
ting the MC1 control bit by software loads the counter
with the value of the autoreload register and starts the
counter. The counter underflow toggles the (L7) output
pin. The 50% duty cycle signal will be continuously gen-
erated until MC1 is reset by the user program.
www.national.com
18