COP840CJ Datasheet, PDF (23/36 Pages) National Semiconductor (TI) – 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector

Control Registers (Continued)
HC C TPND ENTI IPND BUSY ENI GIE
Bit 7
Bit 0
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table 9 lists
the instructions that effect the HC and the C flags.
TABLE 9. Instructions Effecting HC and C Flags
Instr.
ADC
SUBC
SET C
RESET
C
RRC
HC Flag
Depends on
operands
Depends on
operands
Set
Set
Depends on
operands
C Flag
Depends on
operands
Depends on
operands
Set
Set
Depends on
operands
CNTRL2 REGISTER (ADDRESS 00CC)
MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF unused
R/W R/W R/W R/W R/O R/W R/O
Bit 7
Bit 0
MC3 Modulator/Timer Control Bit
MC2 Modulator/Timer Control Bit
MC1 Modulator/Timer Control Bit
CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)
WDREN REGISTER (ADDRESS 00CD)
WDRENWATCHDOG Reset Enable Bit (Write Once Only)
UNUSED
Bit 7
WDREN
Bit 0
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
ADDRESS
00–6F
70–7F
80–BF
C0–C7
C8
TABLE 10. Memory Map
CONTENTS
On-Chip RAM bytes (112 bytes)
Unused RAM address
(Reads as all ones)
Unused RAM address
(Reads Undefined Data)
Reserved
MIWU Edge Select Register
(Reg:WKEDG)
ADDRESS
CONTENTS
C9
MIWU Enable Register (Reg:WKEN)
CA
MIWU Pending Register (Reg:WKPND)
CB
Reserved
CC
Control2 Register (CNTRL2)
CD
WATCHDOG Register (WDREG)
CE
WATCHDOG Counter (WDCNT)
CF
Modulator Reload (MODRL)
D0
Port L Data Register
D1
Port L Configuration Register
D2
Port L input Pins (read only)
D3
Reserved for Port L
D4
Port G Data Register
D5
Port G Configuration Register
D6
Port G Input pins (read only)
D7
Port I Input pins (read only)
D8–DB
Reserved for Port C
DC
Port D Data Register
DD–DF
Reserved for Port D
E0–EF
On-Chip Functions and Registers
E0–E7
Reserved for Future Parts
E8
Reserved
E9
MICROWIRE Shift Register
EA
Timer Lower Byte
EB
Timer Upper Byte
EC
Timer1 Autoreload Register Lower Byte
ED
Timer1 Autoreload Register Upper Byte
EE
CNTRL1 Control Register
EF
PSW Register
F0–FF
On-Chip RAM mapped as Registers
FC
X Register
FD
SP Register
FE
B Register
Reading other unused memory locations will return unde-
fined data.
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
REGISTER INDIRECT
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the B or X pointer.
REGISTER INDIRECT WITH AUTO POST
INCREMENT OR DECREMENT
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automati-
cally post increments or post decrements the B or X pointer
after executing the instruction.
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