UPD98404 Datasheet, PDF (24/36 Pages) NEC – ADVANCED ATM SONET FRAMER

µPD98404
(ii) Write timing
Parameter
Symbol
Address setup time (to CS_B↓)
tSADCS
R/W_B setup time (to CS_B↓)
tSRWCS
Data setup time (to CS_B↓)
tSDACS
Address hold time (to CS_B↑)
tHADCSW
R/W_B hold time (to CS_B↑)
tHRWCSW
Data hold time (to CS_B↑)
tHDACS
CS_B pulse width
tWCS
Remark tCYTK is the cycle of the TCLK clock.
Condition
MIN.
TYP.
MAX.
Unit
10
ns
10
ns
10
ns
10
ns
10
ns
10
ns
4 × tCYTK
ns
MADD0-MADD6
CS_B
MD0-MD7
tSADDS
tSDACS
tWCS
Data
tHADCSW
tHDACS
DS_B
R/W_B
tSRWCS
tHRWCSW
Caution If the device is reset via software by setting the CMR2 register, do not read or write all the registers
for the duration of at least “20 x TCLK clock cycle (tCYTK)” from that write cycle. Otherwise, the
registers may not be read or written correctly.
24
Data Sheet S11822EJ4V0DS00