UPD98404 Datasheet, PDF (10/36 Pages) NEC – ADVANCED ATM SONET FRAMER

µPD98404
Pin name Pin No.
TFC
26
I/O level
TTL*
REFCLK
28
TTL*
PSEL0,
PSEL1
69, 70
TTL*
AIN1
31
PMDALM
76
Analog
TTL*
PHYALM0- 10-12
PHYALM2
TTL*
RxFP
74
TTL*
(2/3)
I/O
Function
I Parallel transmit clock input. When PSEL [1:0] is set to 1X to select
parallel mode, this pin inputs a parallel transmit clock of 19.44 MHz.
If the TxCL bits [1:0] of the MDR1 register are set to 10 in the serial
mode with PSEL[1:0] = “00”, input the 19.44 MHz source clock of the
internal clock synthesizer PLL.
I Reference clock input. This pin supplies a system clock of 19.44
MHz to the internal clock recovery/synthesizer. Always input this
clock.
I PMD interface mode select input. These pins select the interface
mode of the PMD layer to be used.
PSEL [1:0] = 00 :Serial mode. The clock generated by the internal
clock recovery/synthesizer PLL is used for
transmission and reception.
PSEL [1:0] = 01 :Serial mode. The clock input of the external
RCIT/RCIC and TFKT/TFKC is used for
transmission and reception.
PSEL [1:0] = 1x:Parallel mode. The clock input of RPC and TFC is
used.
O This pin connects the loop filter of the internal synthesizer PLL.
Leave open.
I PMD layer alarm signal input. The signal level of this pin is reflected
in the state bit of an internal register. The transition of the bit can be
used as an interrupt source. The state signal from a peripheral
device is input.
O PHY layer alarm detection signal output. These pins output a signal
indicating that an internally monitored error state (PMDALM,
CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS,
Line RDI, or Path RDI) has been detected. The pins can output an
error either singly or in combination. The type of the error to be
indicated is selected by setting the internal AMPR, AMR1, and AMR2
registers. For details on use, refer to 3.5 Alarm Report Pins
(PHYALM[2:0], PMDALM) in µPD98404 User’s Manual
(S11821E).
O Frame pulse output for the receive side (8 kHz). This pin outputs a
pulse signal at one-clock intervals in sync with the RCL clock in the
frame synchronization state.
10
Data Sheet S11822EJ4V0DS00