UPD98404 Datasheet, PDF (19/36 Pages) NEC – ADVANCED ATM SONET FRAMER

µPD98404
Management Interface
a) Internal register read
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Address setup time (to DS_B↓ [RD_B↓])
tSADDS
10
ns
CS_B setup time (to DS_B↓ [RD_B↓])
tSCSDS
5
9 × tCYTK
ns
R/W_B[WR_B] setup time
(to DS_B↓ [RD_B↓])
tSRWDS
5
ns
Address hold time (to DS_B↑ [RD_B↑])
tHADDS
4
ns
CS_B hold time (to DS_B↑ [RD_B↑])
tHCSDS
0
ns
R/W_B [WR_B] hold time
(to DS_B↑ [RD_B↑])
tHRWDS
4
ns
DS_B↓ [RD_B↓] → ACK_B [RDY_B]
output delay time
tVAKDS Load capacity = 50 pF
15
ns
DS_B↓ [RD_B↓] → data output delay
time
tVDADS Load capacity = 50 pF
20
ns
DS_B↑ [RD_B↑] → ACK_B [RDY_B] float tIAKDSR Load capacity = 50 pF
5
delay time
30
ns
DS_B↑ [RD_B↑] → data float delay time
tIDADS Load capacity = 50 pF
15
45
ns
ACK↓ → data output delay time
DS_B[RD_B] pulse width^Note
tDDAAK Load capacity = 50 pF
tWDS
50
10
ns
ns
DS_B↑[RD_B↑]→DS_B↓[RD_B↓]↓
recovery time
tDSINT
4 × tCYTK
ns
Note tWDS defines the time during which the µPD98404 can recognize DS_B [RD_B] as a low level, and does not
define the pulse width of DS_B [RD_B] with which data can be accurately read.
The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low differs
depending on the register to be accessed. Make DS_B [RD_B] high after confirming that ACK_B [RDY_B].
The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low is “4 x
TCLK clock cycle (tCYTK)” at best. So that any register can be read without using ACK_B [RDY_B], widen
the pulse width of DS_B [RD_B] to at least to “4 x TCLK clock cycle”.
Remark tCYTK is the cycle of the TCLK clock.
Data Sheet S11822EJ4V0DS00
19