UPD98404 Datasheet, PDF (21/36 Pages) NEC – ADVANCED ATM SONET FRAMER

µPD98404
b) Internal register write
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Address setup time (to DS_B↓ [WR_B↓])
tSADDS
10
ns
CS_B setup time (to DS_B↓ [WR_B↓])
tSCSDS
5
9 × tCYTK
ns
R/W_B[RD_B] setup time
(to DS_B↓ [WR_B↓])
tSRWDS
5
ns
Data setup time (to DS_B↑ [WR_B↑])
tSDADS
15
ns
Address hold time (to DS_B↑ [WR_B↑])
tHADDS
4
ns
CS_B hold time (to DS_B↑ [WR_B↑])
tHCSDS
0
ns
R/W_B [WR_B] hold time
(to DS_B↑ [WR_B↑])
tHRWDS
4
ns
Data hold time (to DS_B↑ [WR_B↑])
tHDADS
4
ns
DS_B↓ [WR_B↓] → ACK_B [RDY_B]
output delay time
tVAKDS Load capacity = 50 pF
15
ns
DS_B↑ [WR_B↑] → ACK_B [RDY_B]
float delay time
DS_B [WR_B] pulse width^Note
DS_B↑[WR_B↑]→DS_B↓[WR_B↓]↓
recovery time
tIAKDSW Load capacity = 50 pF
tWDS
tDSINT
50
4 × tCYTK
10
ns
ns
ns
Note tWDS defines the time during which the µPD98404 can recognize DS_B [WR_B] as a low level, and does not
define the pulse width of DS_B [WR_B] with which data can be accurately read.
The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low differs
depending on the register to be accessed. Make DS_B [WR_B] high after confirming that ACK_B [RDY_B]
has gone low.
The time required for the µPD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low is “4 x
TCLK clock cycle (tCYTK)” at best. So that any register can be write without using ACK_B [RDY_B], widen
the pulse width of DS_B [WR_B] to at least to “4 x TCLK clock cycle”.
Remark tCYTK is the cycle of the TCLK clock.
Data Sheet S11822EJ4V0DS00
21