MT40A512M16JY-083E Datasheet, PDF (91/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Multipurpose Register
5. Redirect all subsequent WRITE commands to specific MPRx location.
6. Issue WR or WRA command:
a. BA1 and BA0 indicate MPRx location
1. 00 = MPR0
2. 01 = MPR1
3. 10 = MPR2
4. 11 = MPR3
b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0].
c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t
Care."
7. ^tWR_MPR must be satisfied to complete MPR WRITE.
8. Steps 5 through 7 may be repeated to write additional MPRx locations.
9. After the last MPRx WRITE, ^tMPRR must be satisfied prior to exiting.
10. Issue MRS command to exit MPR mode; MR3[2] = 0.
11. When the ^tMOD sequence is completed, the DRAM is ready for normal operation
from the core (such as ACT).
MPR WRITE Waveforms
The following waveforms show MPR write accesses.
Figure 33: MPR WRITE and WRITE-to-READ Timing
CK_c
CK_t
Command
Address
T0
Ta0
Ta1
MPR Enable
PREA
MRS¹
DES
t_RP
t_MOD
Valid
Valid
Valid
Tb0
Tc0
Tc1
WRITE
Add²
DES
DES
t_{WR_MPR}
Valid
Valid
Tc2
READ
Add
Td0
DES
Valid
Td1
DES
Valid
Td2
DES
Valid
Td3
DES
Add²
Td4
DES
Valid
Td5
DES
Valid
CKE
DQS_t,
DQS_c
DQ
PL³ + AL + CL
UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7
Time Break
Don’t Care
Notes:
1. Multipurpose registers read/write enable (MR3 A2 = 1).
2. Address setting:
BA1 and BA0 indicate the MPR location
A10 and other address pins are "Don’t Care"
3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena-
bled.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
91
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