MT40A512M16JY-083E Datasheet, PDF (222/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 167: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)
T0
T1
T2
T9
T10
T11
T17
T18
T19
T20
T21
T22
T23
CK_c
CK_t
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
t_WPRE
t_WPST
DQ
AL = 10
CWL = 9
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 19
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1^tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
WRITE Operation Followed by Another WRITE Operation
Figure 168: Consecutive WRITE (BL8) with 1^tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DES
DES
t_{CCD_S = 4}
DES
WRITE
DES
BGb
Bank
Col b
DQS_t,
DQS_c
DQ
WL = AL + CWL = 9
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_WR
4 Clocks
t_WTR
t_WPRE
t_WPST
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = AL + CWL = 9
Notes: 1. BL8, AL = 0, CWL = 9, Preamble = 1^tCK.
2. DI n (or b) = data-in from column n (or column b).
Time Break
Transitioning Data
Don’t Care
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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