MT40A512M16JY-083E Datasheet, PDF (4/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Features
READ Preamble Training ............................................................................................................................ 55
Temperature-Controlled Refresh ................................................................................................................. 55
Command Address Latency ........................................................................................................................ 55
Internal V_REF Monitor ................................................................................................................................. 55
Maximum Power Savings Mode ................................................................................................................... 56
Mode Register 5 .............................................................................................................................................. 57
Data Bus Inversion ..................................................................................................................................... 58
Data Mask .................................................................................................................................................. 59
CA Parity Persistent Error Mode .................................................................................................................. 59
ODT Input Buffer for Power-Down .............................................................................................................. 59
CA Parity Error Status ................................................................................................................................. 59
CRC Error Status ......................................................................................................................................... 59
CA Parity Latency Mode .............................................................................................................................. 59
Mode Register 6 .............................................................................................................................................. 60
t_{CCD_L Programming ................................................................................................................................. 61}
V_REFDQ Calibration Enable .......................................................................................................................... 61
V_REFDQ Calibration Range ........................................................................................................................... 61
V_REFDQ Calibration Value ............................................................................................................................ 61
Truth Tables ................................................................................................................................................... 62
NOP Command .............................................................................................................................................. 65
DESELECT Command .................................................................................................................................... 65
DLL-Off Mode ................................................................................................................................................ 65
DLL-On/Off Switching Procedures .................................................................................................................. 67
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 67
DLL-Off to DLL-On Procedure .................................................................................................................... 68
Input Clock Frequency Change ....................................................................................................................... 69
Write Leveling ................................................................................................................................................ 70
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 72
Procedure Description ................................................................................................................................ 73
Write Leveling Mode Exit ............................................................................................................................ 74
Command Address Latency ............................................................................................................................ 75
Low-Power Auto Self Refresh Mode ................................................................................................................. 80
Manual Self Refresh Mode .......................................................................................................................... 80
Multipurpose Register .................................................................................................................................... 82
MPR Reads ................................................................................................................................................. 83
MPR Readout Format ................................................................................................................................. 85
MPR Readout Serial Format ........................................................................................................................ 85
MPR Readout Parallel Format ..................................................................................................................... 86
MPR Readout Staggered Format .................................................................................................................. 87
MPR READ Waveforms ............................................................................................................................... 88
MPR Writes ................................................................................................................................................ 90
MPR WRITE Waveforms .............................................................................................................................. 91
MPR REFRESH Waveforms ......................................................................................................................... 92
Gear-Down Mode ........................................................................................................................................... 95
Maximum Power-Saving Mode ........................................................................................................................ 98
Maximum Power-Saving Mode Entry ........................................................................................................... 98
Maximum Power-Saving Mode Entry in PDA ............................................................................................... 99
CKE Transition During Maximum Power-Saving Mode ................................................................................. 99
Maximum Power-Saving Mode Exit ............................................................................................................. 99
Command/Address Parity .............................................................................................................................. 101
Per-DRAM Addressability .............................................................................................................................. 109
V_REFDQ Calibration ........................................................................................................................................ 112
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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