MT40A512M16JY-083E Datasheet, PDF (72/358 Pages) Micron Technology – Automotive DDR4 SDRAM

8Gb: x8, x16 Automotive DDR4 SDRAM
Write Leveling
Figure 17: Write Leveling Concept, Example 2
CK_c
CK_t
CK_c
CK_t
CK_c
CK_t
DQS_t/
t_WLS
111 11111 11 111 1111 1
t_WLH
0 000 000 000 000
t_WLS t_WLH
0 0 0 0 0 0 0 _{X XX XXX} 11 111 1111 1
DQS_c
t_WLO
DQ (CK 0 to 1)
DQ (CK 1 to 0)
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode
The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is fin-
ished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling
Procedures table). Note that in write leveling mode, only DQS terminations are activa-
ted and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TER-
MINATION Function in Leveling Mode table).
Table 25: MR Settings for Leveling Procedures
Function
Write leveling enable
Output buffer mode (Q off)
MR1
A7
A12
Enable
1
0
Disable
0
1
Table 26: DRAM TERMINATION Function in Leveling Mode
ODT Pin at DRAM
R_TT(NOM) with ODT HIGH
R_TT(Park) with ODT LOW
DQS_t/DQS_c Termination
On
On
DQ Termination
Off
Off
Notes:
1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1
and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] =
0), all R_TT(NOM) and R_TT(Park) settings are supported.
2. R_TT(WR) is not allowed in write leveling mode and must be set to disable prior to enter-
ing write leveling mode.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. C 3/17 EN
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