N25Q064A13ESF40G Datasheet, PDF (50/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

64Mb, 3V, Multiple I/O Serial Flash Memory
ERASE Operations
ERASE Operations
SUBSECTOR ERASE Command
To execute the SUBSECTOR ERASE command (and set the selected subsector bits set to
FFh), the WRITE ENABLE command must be issued to set the write enable latch bit to
1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been
latched in, after which it must be driven HIGH. The command code is input on DQ0,
followed by three address bytes; any address within the subsector is valid. Each address
bit is latched in during the rising edge of the clock. When S# is driven HIGH, the opera-
tion, which is self-timed, is initiated; its duration is ^tSSE. The operation can be suspen-
ded and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME
commands, respectively.
If the write enable latch bit is not set, the device ignores the SUBSECTOR ERASE com-
mand and no error bits are set to indicate operation failure.
When the operation is in progress, the write in progress bit is set to 1. The write enable
latch bit is cleared to 0, whether the operation is successful or not. The status register
and flag status register can be polled for the operation status. When the operation com-
pletes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and the erase error bit is set
to 1. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1. When a command is applied
to a protected subsector, the command is not executed. Instead, the write enable latch
bit remains set to 1, and flag status register bits 1 and 5 are set.
SECTOR ERASE Command
To execute the SECTOR ERASE command (and set selected sector bits to FFh), the
WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is
driven LOW and held LOW until the eighth bit of the last data byte has been latched in,
after which it must be driven HIGH. The command code is input on DQ0, followed by
three address bytes; any address within the sector is valid. Each address bit is latched in
during the rising edge of the clock. When S# is driven HIGH, the operation, which is
self-timed, is initiated; its duration is ^tSE. The operation can be suspended and resumed
by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, re-
spectively.
If the write enable latch bit is not set, the device ignores the SECTOR ERASE command
and no error bits are set to indicate operation failure.
When the operation is in progress, the write in progress bit is set to 1 and the write ena-
ble latch bit is cleared to 0, whether the operation is successful or not. The status regis-
ter and flag status register can be polled for the operation status. When the operation
completes, the write in progress bit is cleared to 0.
If the operation times out, the write enable latch bit is reset and erase error bit is set to
1. If S# is not driven HIGH, the command is not executed, flag status register error bits
are not set, and the write enable latch remains set to 1. When a command is applied to a
protected sector, the command is not executed. Instead, the write enable latch bit re-
mains set to 1, and flag status register bits 1 and 5 are set.
PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
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