English
Language : 

N25Q064A13ESF40G Datasheet, PDF (33/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase
64Mb, 3V, Multiple I/O Serial Flash Memory
READ REGISTER and WRITE REGISTER Operations
Figure 13: READ LOCK REGISTER Command
Extended
0
C
DQ[0]
DQ1
Command
MSB
High-Z
7
8
LSB
A[MAX]
Dual
0
C
DQ[1:0]
Command
MSB
3
4
LSB
A[MAX]
Cx
A[MIN]
DOUT
MSB
Cx
DOUT
A[MIN]
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
LSB
DOUT
DOUT
LSB
DOUT
DOUT
Quad
C
0
1
2
Cx
DQ[3:0]
Command
MSB
Note:
LSB
A[MAX]
A[MIN]
DOUT
MSB
LSB
DOUT
DOUT
1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1).
For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2).
For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4).
Don’t Care
WRITE LOCK REGISTER Command
To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must
be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until
the eighth bit of the last data byte has been latched in, after which it must be driven
HIGH. The command code is input on DQn, followed by three address bytes that point
to a location in the sector, and then one data byte that contains the desired settings for
lock register bits 0 and 1. Each address bit is latched in during the rising edge of the
clock.
When execution is complete, the write enable latch bit is cleared within tSHSL2 and no
error bits are set. Because lock register bits are volatile, change to the bits is immediate.
WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef-
fect. If S# is not driven HIGH, the command is not executed, flag status register error
bits are not set, and the write enable latch remains set to 1.
PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
33
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.