N25Q064A13ESF40G Datasheet, PDF(21/81 Page) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

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N25Q064A13ESF40G Datasheet, PDF (21/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

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Status Register

64Mb, 3V, Multiple I/O Serial Flash Memory

Nonvolatile and Volatile Registers

Table 9: Status Register Bit Definitions

Note 1 applies to entire table

Bit Name

7 Status register

write enable/disable

5 Top/bottom

6, 4:2 Block protect 3â0

1 Write enable latch

0 Write in progress

Settings

Description

0 = Enabled

1 = Disabled

Nonvolatile bit: Used with the W/VPP signal to enable or

disable writing to the status register.

0 = Top

1 = Bottom

Nonvolatile bit: Determines whether the protected mem-

ory area defined by the block protect bits starts from the

top or bottom of the memory array.

See Protected Area

Sizes â Upper Area

and Lower Area

tables in Device

Protection

Nonvolatile bit: Defines memory to be software protec-

ted against PROGRAM or ERASE operations. When one or

more block protect bits is set to 1, a designated memory

area is protected from PROGRAM and ERASE operations.

0 = Cleared (Default) Volatile bit: The device always powers up with this bit

1 = Set

cleared to prevent inadvertent WRITE STATUS REGISTER,

PROGRAM, or ERASE operations. To enable these opera-

tions, the WRITE ENABLE operation must be executed first

to set this bit.

0 = Ready

1 = Busy

Volatile bit: Indicates if one of the following command cy-

cles is in progress:

WRITE STATUS REGISTER

WRITE NONVOLATILE CONFIGURATION REGISTER

PROGRAM

ERASE

Notes

Notes:

1. Bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REG-

ISTER commands, respectively.

2. Volatile bits are cleared to 0 by a power cycle or reset.

3. The status register write enable/disable bit, combined with the W#/VPP signal as descri-

bed in the Signal Descriptions, provides hardware data protection for the device as fol-

lows: When the enable/disable bit is set to 1, and the W#/VPP signal is driven LOW, the

status register nonvolatile bits become read-only and the WRITE STATUS REGISTER oper-

ation will not execute. The only way to exit this hardware-protected mode is to drive

W#/VPP HIGH.

4. See Protected Area Sizes tables in Device Protection. The BULK ERASE command is exe-

cuted only if all bits are 0.

PDF: 09005aef845665f4

n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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