N25Q064A13ESF40G Datasheet, PDF (4/81 Pages) Micron Technology – Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase

64Mb, 3V, Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 8
Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8
Figure 4: 24-Ball TBGA , 5 x 5 (Balls Down) ....................................................................................................... 9
Figure 5: 24-Ball TBGA, 4 x 6 (Balls Down) ........................................................................................................ 9
Figure 6: Block Diagram ................................................................................................................................ 12
Figure 7: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17
Figure 8: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18
Figure 9: SPI Modes ....................................................................................................................................... 18
Figure 10: Internal Configuration Register ...................................................................................................... 20
Figure 11: READ REGISTER Command .......................................................................................................... 29
Figure 12: WRITE REGISTER Command ......................................................................................................... 31
Figure 13: READ LOCK REGISTER Command ................................................................................................. 33
Figure 14: WRITE LOCK REGISTER Command ............................................................................................... 34
Figure 15: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 36
Figure 16: READ Command ........................................................................................................................... 40
Figure 17: FAST READ Command ................................................................................................................... 40
Figure 18: DUAL OUTPUT FAST READ ........................................................................................................... 41
Figure 19: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 41
Figure 20: QUAD OUTPUT FAST READ Command ......................................................................................... 42
Figure 21: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 42
Figure 22: PAGE PROGRAM Command .......................................................................................................... 44
Figure 23: DUAL INPUT FAST PROGRAM Command ...................................................................................... 45
Figure 24: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 45
Figure 25: QUAD INPUT FAST PROGRAM Command ..................................................................................... 46
Figure 26: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 47
Figure 27: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 49
Figure 28: SUBSECTOR and SECTOR ERASE Command .................................................................................. 51
Figure 29: BULK ERASE Command ................................................................................................................ 52
Figure 30: READ OTP Command .................................................................................................................... 55
Figure 31: PROGRAM OTP Command ............................................................................................................ 57
Figure 32: XIP Mode Directly After Power-On .................................................................................................. 59
Figure 33: Power-Up Timing .......................................................................................................................... 61
Figure 34: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 64
Figure 35: Reset Enable ................................................................................................................................. 64
Figure 36: Serial Input Timing ........................................................................................................................ 64
Figure 37: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 65
Figure 38: Hold Timing .................................................................................................................................. 65
Figure 39: Output Timing .............................................................................................................................. 66
Figure 40: V_PPH Timing .................................................................................................................................. 66
Figure 41: AC Timing Input/Output Reference Levels ...................................................................................... 68
Figure 42: V-PDFN-8 6mm x 5mm (MLP8) – Package Code: F6 ........................................................................ 72
Figure 43: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 73
Figure 44: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 74
Figure 45: T-PBGA-24b05 6mm x 8mm – Package Code: 14 .............................................................................. 75
Figure 46: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 76
Figure 47: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 77
PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
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