PIC16F627A Datasheet, PDF (99/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

PIC16F627A/628A/648A
14.2.8 SPECIAL FEATURE: DUAL SPEED
OSCILLATOR MODES
A software programmable dual speed Oscillator mode
is provided when the PIC16F627A/628A/648A is con-
figured in the INTOSC Oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz nominal in the INTOSC
mode. Applications that require low current power sav-
ings, but cannot tolerate putting the part into SLEEP,
may use this mode.
There is a time delay associated with the transition
between Fast and Slow oscillator speeds. This Oscilla-
tor Speed Transition delay consists of two existing
clock pulses and eight new speed clock pulses. During
this Clock Speed Transition Delay the System Clock is
halted causing the processor to be frozen in time. Dur-
ing this delay the Program Counter and the Clock Out
stop.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 4.2.2.6, Register 4-6.
14.3 RESET
The PIC16F627A/628A/648A differentiates between
various kinds of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) WDT Reset (normal operation)
e) WDT wake-up (SLEEP)
f) Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, Brown-out Reset,
MCLR Reset, WDT Reset and MCLR Reset during
SLEEP. They are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. TO and PD bits are set or cleared differently in
different RESET situations as indicated in Table 14-4.
These bits are used in software to determine the nature
of the RESET. See Table 14-7 for a full description of
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.
FIGURE 14-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR/
VPP Pin
VDD
Schmitt Trigger Input
WDT
Module
VDD rise
detect
SLEEP
WDT
Time out
Reset
Power-on Reset
Brown-out
detect Reset
S
BOREN
OST/PWRT
OST
10-bit Ripple-counter
OSC1/
R
CLKIN
Pin
PWRT
On-chip⁽¹⁾
OSC
10-bit Ripple-counter
Q
Chip_Reset
Q
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the INTOSC/RC oscillator.
See Table 14-3 for time out situations.
 2002 Microchip Technology Inc.
Preliminary
DS40044A-page 97