PIC16F627A Datasheet, PDF (109/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

PIC16F627A/628A/648A
FIGURE 14-16:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
Watchdog
Timer
WDT
Enable Bit
0
M
U
1X
PSA
WDT POSTSCALER/
TMR0 PRESCALER
8
8 to 1 MUX
PS<2:0>
3
To TMR0
(Figure 6-1)
0
1
MUX
PSA
Note:
WDT
Time out
T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
RESETS
2007h
Config.
bits
LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0
81h, 181h OPTION RBPU INTEDG T0CS T0SE
PSA
PS2
PS1
PS0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Note: Shaded cells are not used by the Watchdog Timer.
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
14.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or hi-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators, and VREF should be disabled. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
Note:
It should be noted that a RESET generated
by a WDT time out does not drive MCLR
pin low.
 2002 Microchip Technology Inc.
Preliminary
DS40044A-page 107