PIC16F627A Datasheet, PDF (82/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

PIC16F627A/628A/648A
FIGURE 12-9:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
RB1/RX/DT (PIN)
START
BIT _{BIT0 BIT1}
RCV SHIFT REG
START
BIT8 STOP BIT BIT0
BIT
BIT8 STOP
BIT
RCV BUFFER REG
READ RCV
BUFFER REG
RCREG
BIT8 = 0, DATA BYTE
BIT8 = 1, ADDRESS BYTE ^{WORD 1}
RCREG
RCIF
(INTERRUPT FLAG)
ADEN = 1
'1'
'1'
(ADDRESS MATCH
ENABLE)
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
RB1/RX/DT (PIN)
START
BIT BIT0 BIT1
START
BIT8 STOP BIT BIT0
BIT
BIT8 STOP
BIT
RCV SHIFT
REG
RCV BUFFER REG
READ RCV
BIT8 = 1, ADDRESS BYTE ^{WORD 1}
RCREG
BIT8 = 0, DATA BYTE
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
'1'
'1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
FIGURE 12-11:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
RB1/RX/DT (PIN)
START
BIT BIT0 BIT1
START
BIT8 STOP BIT BIT0
BIT
BIT8 STOP
BIT
RCV SHIFT
REG
RCV BUFFER REG
READ RCV
BUFFER REG
BIT8 = 1, ADDRESS BYTE ^{WORD 1} BIT8 = 0, DATA BYTE ^{WORD 2}
RCREG
RCREG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN
(ADDRESS MATCH
ENABLE)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.
DS40044A-page 80
Preliminary
 2002 Microchip Technology Inc.