PIC16F627A Datasheet, PDF(110/168 Page) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

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PIC16F627A Datasheet, PDF (110/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

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PIC16F627A/628A/648A

14.8.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin

2. Watchdog Timer wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin, RB Port change, or

any Peripheral Interrupt.

The first event will cause a device RESET. The two lat-

ter events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device RESET.

PD bit, which is set on power-up is cleared when

SLEEP is invoked. TO bit is cleared if WDT wake-up

occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will not

enter SLEEP. The SLEEP instruction is

executed as a NOP instruction.

The WDT is cleared when the device wakes up from

SLEEP, regardless of the source of wake-up.

FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT

OSC1

CLKOUT(4)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Tost(2)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Inst(PC) = SLEEP

Inst(PC - 1)

PC+1

Inst(PC + 1)

SLEEP

PC+2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Interrupt Latency

(Note 2)

PC+2

Inst(PC + 2)

Inst(PC + 1)

PC + 2

Dummy cycle

0004h

Inst(0004h)

Dummy cycle

0005h

Inst(0005h)

Inst(0004h)

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale). Approximately 1 Âµs delay will be there for RC Osc mode.

3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue

in-line.

4: CLKOUT is not available in these Osc modes, but shown here for timing reference.

14.9 Code Protection

With the Code Protect bit is cleared (Code Protect

enabled) the contents of the program memory locations

are read out as â00â. See Programing Specification,

DS41196, for details.

Note:

Only a Bulk Erase function can set the CP

and CPD bits by turning off the code pro-

tection. The entire data EEPROM and

FLASH program memory will be erased to

turn the code protection off.

14.10 User ID Locations

Four memory locations (2000h-2003h) are designated

as user ID locations where the user can store check-

sum or other code-identification numbers. These loca-

tions are not accessible during normal execution but

are readable and writable during program/verify. Only

the Least Significant 4 bits of the user ID locations are

used.

DS40044A-page 108

Preliminary

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