PIC16F627A Datasheet, PDF (70/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

PIC16F627A/628A/648A
EXAMPLE 11-1: VOLTAGE REFERENCE
CONFIGURATION
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
0x02
;4 Inputs Muxed
CMCON
;to 2 comps.
STATUS,RP0 ;go to Bank 1
0x07
;RA3-RA0 are
TRISA
;outputs
0xA6
;enable VREF
VRCON
;low range set VR<3:0>=6
STATUS,RP0 ;go to Bank 0
DELAY10 ;10µs delay
11.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 11-1) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
tested absolute accuracy of the Voltage Reference can
be found in Table 17-3.
11.3 Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
11.4 Effects of a RESET
A device RESET disables the Voltage Reference by
clearing bit VREN (VRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
11.5 Connection Considerations
The Voltage Reference Module operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 11-2 shows an example buffering
technique.
FIGURE 11-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
VREF
Module
R⁽¹⁾
RA2
Opamp
+
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
RESETS
9Fh
1Fh
85h
Note:
VRCON VREN VROE VRR
—
VR3
VR2
VR1
VR0 000- 0000 000- 0000
CMCON C2OUT C1OUT C2INV C1INV CIS
CM2 CM1 CM0 0000 0000 0000 0000
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
— = Unimplemented, read as ‘0’.
DS40044A-page 68
Preliminary
 2002 Microchip Technology Inc.