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PIC16F627A Datasheet, PDF (69/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers
PIC16F627A/628A/648A
11.0 VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 11-1. The block diagram
is given in Figure 11-1.
11.1 Voltage Reference Configuration
The Voltage Reference can output 16 distinct voltage
levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1:
VREF = V-----R---<----3---:-0---->- × VDD
24
if VRR = 0:
VREF
=


VDD
×
14--
+
V-----R---<----3---:-0---->-
32
×
VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 17-3). Example 11-1 demonstrates how Voltage
Reference is configured for an output voltage of 1.25V
with VDD = 5.0V.
REGISTER 11-1:
VRCON REGISTER (ADDRESS: 9Fh)
R/W-0 R/W-0 R/W-0
U-0
VREN
VROE
VRR
—
bit 7
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
VRR: VREF Range selection
1 = Low Range
0 = High Range
Unimplemented: Read as '0'
VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: VREF = (VR<3:0>/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
FIGURE 11-1:
VREN
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
8R
R
R
R
R
VREF
Note: R is defined in Table 17-3.
16-1 Analog Mux
8R
VRR
VSS
VSS
VR3
(From VRCON<3:0>)
VR0
 2002 Microchip Technology Inc.
Preliminary
DS40044A-page 67