PIC16F627A Datasheet, PDF (53/168 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontrollers

PIC16F627A/628A/648A
7.4 Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). It will con-
tinue to run during SLEEP. It is primarily intended for a
32.768 kHz watch crystal. Table 7-1 shows the capaci-
tor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Freq
C1
C2
32.768 kHz
15 pF
15 pF
These values are for design guidance only.
Consult AN826 (DS00826) for further information
on Crystal/Capacitor Selection.
7.5 Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will RESET Timer1.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Timer1 must be configured for either timer or synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
7.6 Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.7 Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Value on
POR
Value on
all other
RESETS
0Bh, 8Bh, INTCON GIE PEIE
10Bh, 18Bh
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x
0Ch
PIR1
EEIF CMIF RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000
8Ch
PIE1
EEIE CMIE RCIE
TXIE
—
CCP1IE TMR2IE TMR1IE 0000 -000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
10h
T1CON
—
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
0000 000u
0000 -000
0000 -000
uuuu uuuu
uuuu uuuu
--uu uuuu
 2002 Microchip Technology Inc.
Preliminary
DS40044A-page 51