PIC24F04KA201 Datasheet, PDF (94/224 Pages) Microchip Technology – 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology

PIC24F04KA201 FAMILY
9.2.2 IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Selective Peripheral Module Control”).
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAV instruction or
the first instruction in the ISR.
9.2.3 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
9.2.4 DEEP SLEEP MODE
In PIC24F04KA201 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available, without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
9.2.4.1 Entering Deep Sleep Mode
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a SLEEP
instruction (PWRSAV #SLEEP_MODE) within one instruc-
tion cycle to minimize the chance that Deep Sleep will
be spuriously entered.
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode.
Note:
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 TCY
after clearing the RELEASE bit.
The sequence to enter Deep Sleep mode is:
1. If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see
Section 9.2.4.5 “Deep Sleep WDT” for
details).
2. If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).
3. If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
4. Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
5. Enter Deep Sleep mode by issuing 3 NOP
commands and then a PWRSAV #0 instruction.
Any time the DSEN bit is set, all bits in the DSWSRC
register will be automatically cleared.
9.2.4.2 Exiting Deep Sleep Mode
Deep Sleep mode exits on any one of the following events:
• POR event on VDD supply. If there is no DSBOR
circuit to re-arm the VDD supply POR circuit, the
external VDD supply must be lowered to the
natural arming voltage of the POR circuit.
• DSWDT time-out. When the DSWDT timer times
out, the device exits Deep Sleep.
• Assertion (‘0’) of the MCLR pin.
• Assertion of the INT0 pin (if the interrupt was
enabled before Deep Sleep mode was entered).
The polarity configuration is used to determine the
assertion level (‘0’ or ‘1’) of the pin that will cause
an exit from Deep Sleep mode. Exiting from Deep
Sleep mode requires a change on the INT0 pin
while in Deep Sleep mode.
DS39937B-page 92
Preliminary
© 2009 Microchip Technology Inc.