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PIC24F04KA201 Datasheet, PDF (47/224 Pages) Microchip Technology – 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology | |||
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PIC24F04KA201 FAMILY
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
WR
WREN
WRERR PGMONLY
â
â
â
bit 15
U-0
â
bit 8
U-0
â
bit 7
R/W-0
ERASE
R/W-0
R/W-0
NVMOP5(1) NVMOP4(1)
R/W-0
R/W-0
NVMOP3(1) NVMOP2(1)
R/W-0
NVMOP1(1)
R/W-0
NVMOP0(1)
bit 0
Legend:
-n = Value at POR
â0â = Bit is cleared
SO = Settable Only bit
â1â = Bit is set
x = Bit is unknown
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as â0â
bit 15
bit 14
bit 13
bit 12
bit 11-7
bit 6
bit 5-0
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
PGMONLY: Program Only Enable bit
Unimplemented: Read as â0â
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<5:0> on the next WR command
0 = Perform the program operation specified by NVMOP<5:0> on the next WR command
NVMOP<5:0>: Programming Operation Command Byte bits(1)
Erase Operations (when ERASE bit is â1â):
1010xx = Erase entire boot block (including code-protected boot block)(2)
1001xx = Erase entire memory (including boot block, configuration block, general block)(2)
011010 = Program/erase 4 rows of Flash memory(3)
011001 = Program/erase 2 rows of Flash memory(3)
011000 = Program/erase 1 row of Flash memory(3)
0101xx = Erase entire configuration block (except code protection bits)
0011xx = Erase entire general memory block programming operations
Note 1: All other combinations of NVMOP<5:0> are no operation.
2: Available in ICSP⢠mode only. Refer to device programming specification.
3: The address in the Table Pointer decides which rows will be erased.
© 2009 Microchip Technology Inc.
Preliminary
DS39937B-page 45
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