PIC24F04KA201 Datasheet, PDF (45/224 Pages) Microchip Technology – 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology

PIC24F04KA201 FAMILY
5.0 FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on Flash
programming, refer to the “PIC24F Family
Reference Manual”, Section 4. “Program
Memory” (DS39715).
The PIC24F04KA201 family of devices contains
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable when operating with VDD over
1.8V.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self Programming (RTSP)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24FXXXX device to be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for the programming clock
and programming data (which are named PGCx and
PGDx, respectively), and three other lines for power
(VDD), ground (VSS) and Master Clear/Program Mode
Entry Voltage (MCLR/VPP). This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or custom firmware to be programmed.
Real-Time Streaming Protocol (RTSP) is accomplished
using TBLRD (table read) and TBLWT (table write)
instructions. With RTSP, the user may write program
memory data in blocks of 32 instructions (96 bytes) at
a time, and erase program memory in blocks of 32, 64
and 128 instructions (96,192 and 384 bytes) at a time.
The NVMOP<1:0> (NVMCON<1:0>) bits decide the
erase block size.
5.1 Table Instructions and Flash
Programming
Regardless of the method used, Flash memory
programming is done with the table read and write
instructions. These allow direct read and write access to
the program memory space from the data memory while
the device is in normal operating mode. The 24-bit target
address in the program memory is formed using the
TBLPAG<7:0> bits and the Effective Address (EA) from
a W register, specified in the table instruction, as
depicted in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits<15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits<23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program
0
Program Counter
0
Counter
Using
Table
1/0 TBLPAG Reg
Instruction
8 Bits
Working Reg EA
16 Bits
User/Configuration
Space Select
24-Bit EA
Byte
Select
© 2009 Microchip Technology Inc.
Preliminary
DS39937B-page 43