PIC24F04KA201 Datasheet, PDF (55/224 Pages) Microchip Technology – 14/20-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology

PIC24F04KA201 FAMILY
REGISTER 6-1: RCON: RESET CONTROL REGISTER⁽¹⁾ (CONTINUED)
bit 0
POR: Power-on Reset Flag bit
1 = A Power-up Reset has occurred
0 = A Power-up Reset has not occurred
Note 1:
2:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TABLE 6-1: RESET FLAG BIT OPERATION
Flag Bit
Setting Event
TRAPR (RCON<15>)
Trap Conflict Event
IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access
CM (RCON<9>)
Configuration Mismatch Reset
EXTR (RCON<7>)
MCLR Reset
SWR (RCON<6>)
RESET Instruction
WDTO (RCON<4>)
WDT Time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP Instruction
IDLE (RCON<2>)
PWRSAV #IDLE Instruction
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
DPSLP (RCON<10>)
PWRSAV #SLEEP instruction with DSCON <DSEN> set
Note: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR
POR
POR
POR
POR
PWRSAV Instruction, POR
POR
POR
—
—
POR
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
TABLE 6-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(FNOSC<10:8>)
COSC Control bits
(OSCCON<14:12>)
© 2009 Microchip Technology Inc.
Preliminary
DS39937B-page 53