PIC18F6390_07 Datasheet, PDF (80/414 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISJ⁽²⁾
TRISH⁽²⁾
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ⁽²⁾
LATH⁽²⁾
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ⁽²⁾
PORTH⁽²⁾
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
Legend:
Note 1:
2:
3:
4:
5:
6:
EUSART1 Baud Rate Generator Register Low Byte
0000 0000 61, 201
EUSART1 Receive Register
0000 0000 61, 208
EUSART1 Transmit Register
0000 0000 61, 206
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 61, 198
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 61, 199
—
LCDIP
RC2IP
TX2IP
—
—
—
—
-111 ---- 61, 106
—
LCDIF
RC2IF
TX2IF
—
—
—
—
-000 ---- 61, 100
—
LCDIE
RC2IE
TX2IE
—
—
—
—
-000 ---- 61, 103
OSCFIP
CMIP
—
—
BCLIP
HLVDIP
TMR3IP
CCP2IP 11-- 1111 61, 105
OSCFIF
CMIF
—
—
BCLIF
HLVDIF
TMR3IF
CCP2IF 00-- 0000 61, 99
OSCFIE
CMIE
—
—
BCLIE
HLVDIE
TMR3IE
CCP2IE 00-- 0000 61, 102
—
ADIP
RC1IP
TX1IP
SSPIP
CCP1IP
TMR2IP
TMR1IP -111 1111 61, 104
—
ADIF
RC1IF
TX1IF
SSPIF
CCP1IF
TMR2IF
TMR1IF -000 0000 61, 98
—
INTSRC
ADIE
PLLEN⁽³⁾
RC1IE
—
TX1IE
TUN4
SSPIE
TUN3
CCP1IE
TUN2
TMR2IE
TUN1
TMR1IE -000 0000 61, 101
TUN0 00-0 0000 35, 61
PORTJ Data Direction Register
1111 1111 62, 130
PORTH Data Direction Register
1111 1111 62, 128
—
—
—
PORTG Data Direction Register
---1 1111 62, 126
PORTF Data Direction Register
1111 1111 62, 124
PORTE Data Direction Register
—
—
—
—
1111 ---- 62, 121
PORTD Data Direction Register
1111 1111 62, 119
PORTC Data Direction Register
1111 1111 62, 117
PORTB Data Direction Register
TRISA7⁽⁵⁾ TRISA6⁽⁵⁾ PORTA Data Direction Register
1111 1111 62, 114
1111 1111 62, 111
LATJ Data Output Register
xxxx xxxx 62, 130
LATH Data Output Register
xxxx xxxx 62, 128
—
—
—
LATG Data Output Register
---x xxxx 62, 126
LATF Data Output Register
xxxx xxxx 62, 124
LATE Data Output Register
—
—
—
—
xxxx ---- 62, 121
LATD Data Output Register
xxxx xxxx 62, 119
LATC Data Output Register
xxxx xxxx 62, 117
LATB Data Output Register
LATA7⁽⁵⁾ LATA6⁽⁵⁾ LATA Data Output Register
xxxx xxxx 62, 114
xxxx xxxx 62, 111
Read PORTJ pins, Write PORTJ Data Latch
xxxx xxxx 62, 130
Read PORTH pins, Write PORTH Data Latch
—
—
RG5⁽⁴⁾ Read PORTG pins <4:0>, Write PORTG Data Latch <4:0>
xxxx xxxx 62, 128
--xx xxxx 62, 126
Read PORTF pins, Write PORTF Data Latch
xxxx xxxx 62, 124
Read PORTE pins, Write PORTE Data Latch
—
—
—
—
xxxx ---- 62, 121
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx 62, 119
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx 62, 117
Read PORTB pins, Write PORTB Data Latch
RA7⁽⁵⁾
RA6⁽⁵⁾ Read PORTA pins, Write PORTA Data Latch
xxxx xxxx 62, 114
xx0x 0000 62, 111
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.
DS39629C-page 78
© 2007 Microchip Technology Inc.