PIC18F6390_07 Datasheet, PDF (118/414 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 9-5: PORTC FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
Buffer
Description
RC0/T1OSO/
RC0
0
T13CKI/
1
T1OSO
x
T13CKI
x
RC1/T1OSI/
CCP2
RC1
0
1
T1OSI
x
CCP2⁽¹⁾
0
1
RC2/CCP1/
SEG13
RC2
0
1
CCP1
0
1
SEG13
x
RC3/SCK/SCL
RC3
0
1
SCK
0
1
SCL
0
1
RC4/SDI/SDA
RC4
0
1
SDI
1
SDA
1
1
RC5/SDO/
SEG12
RC5
0
1
SDO
0
SEG12
x
RC6/TX1/CK1
RC6
0
1
TX1
1
O
DIG LATC<0> data output; disabled when Timer1 oscillator is used.
I
ST PORTC<0> data input; disabled when Timer1 oscillator is used.
O
ANA Timer1 oscillator output.
I
ST Timer1/Timer3 clock input.
O
DIG LATC<1> data output; disabled when Timer1 oscillator is used.
I
ST PORTC<1> data input; disabled when Timer1 oscillator is used.
I
ANA Timer1 oscillator input.
O
DIG CCP2 compare output or PWM output; takes priority over digital I/O data.
I
ST CCP2 capture input.
O
DIG LATC<2> data output; disabled when LCD segment enabled.
I
ST PORTC<2> data input.
O
DIG CCP1 compare output or PWM output; takes priority over digital I/O data.
I
ST CCP1 capture input.
O
ANA Segment 13 analog output for LCD.
O
DIG LATC<3> data output.
I
ST PORTC<3> data input.
O
DIG SPI clock output (MSSP module); takes priority over port data.
I
ST SPI clock input (MSSP module).
O
DIG I²C™ clock output (MSSP module); takes priority over port data.
I
ST I²C clock input (MSSP module); input type depends on module setting.
O
DIG LATC<4> data output.
I
ST PORTC<4> data input.
I
ST SPI data input (MSSP module).
O
DIG I²C data output (MSSP module); takes priority over port data.
I
ST I²C data input (MSSP module); input type depends on module setting.
O
DIG LATC<5> data output; disabled when LCD segment enabled.
I
ST PORTC<5> data input.
O
DIG SPI data output (MSSP module); takes priority over port data.
O
ANA Segment 12 analog output for LCD.
O
DIG LATC<6> data output.
I
ST PORTC<6> data input.
O
DIG Synchronous serial data output (EUSART module); takes priority over
port data.
CK1
1
O
DIG Synchronous serial data input (EUSART module). User must configure
as an input.
1
I
ST Synchronous serial clock input (EUSART module).
RC7/RX1/DT1
RC7
0
O
DIG LATC<7> data output.
1
I
ST PORTC<7> data input.
RX1
1
I
ST Asynchronous serial receive data input (EUSART module).
DT1
1
O
DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST Synchronous serial data input (EUSART module). User must configure
as an input.
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for CCP2 (CCP2MX Configuration bit = 1).
DS39629C-page 116
© 2007 Microchip Technology Inc.