PIC18F6390_07 Datasheet, PDF (106/414 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
8.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 8-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0
—
bit 7
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
R/W-1
CCP1IP
R/W-1
TMR2IP
R/W-1
TMR1IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5
RC1IP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4
TX1IP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
DS39629C-page 104
© 2007 Microchip Technology Inc.