PIC18F6390_07 Datasheet, PDF (216/414 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
16.3.2 EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA1<5>), or the Continuous Receive
Enable bit, CREN (RCSTA1<4>). Data is sampled on
the RX1 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH1:SPBRG1 registers for the
appropriate baud rate. Set or clear the BRG16 bit,
as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RC1IE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RC1IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC1IE, was set.
8. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG1 register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 16-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX1/CK1 pin
(SCKP = 0)
RC6/TX1/CK1 pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit ‘0’
‘0’
RC1IF bit
(Interrupt)
Read
RCREG1
Note: Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0.
TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 61
PIE1
—
ADIE
RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61
IPR1
—
ADIP
RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 61
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREG1 EUSART1 Receive Register
61
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON1 ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN 62
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
62
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
DS39629C-page 214
© 2007 Microchip Technology Inc.