PIC18F6390_07 Datasheet, PDF (409/414 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 193
Brown-out Reset (BOR) ........................................... 372
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 194
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 194
Bus Collision During a Start
Condition (SCL = 0) ......................................... 193
Bus Collision During a Start
Condition (SDA Only) ...................................... 192
Bus Collision During a Stop
Condition (Case 1) ........................................... 195
Bus Collision During a Stop
Condition (Case 2) ........................................... 195
Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 374
CLKO and I/O .......................................................... 371
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 69
Example SPI Master Mode (CKE = 0) ..................... 375
Example SPI Master Mode (CKE = 1) ..................... 376
Example SPI Slave Mode (CKE = 0) ....................... 377
Example SPI Slave Mode (CKE = 1) ....................... 378
External Clock (All Modes Except PLL) ................... 369
Fail-Safe Clock Monitor ............................................ 291
High/Low-Voltage Detect Characteristics ................ 366
High-Voltage Detect Operation (VDIRMAG = 1) ...... 254
I²C Bus Data ............................................................ 379
I²C Bus Start/Stop Bits ............................................. 379
I²C Master Mode (7 or 10-Bit Transmission) ........... 188
I²C Master Mode (7-Bit Reception) .......................... 189
I²C Master Mode First Start Bit ................................ 185
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 174
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 179
I²C Slave Mode (10-Bit Transmission) ..................... 175
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 172
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 178
I²C Slave Mode (7-Bit Transmission) ....................... 173
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) ........ 180
I²C Stop Condition Receive or Transmit Mode ........ 190
LCD Interrupt Timing in Quarter-Duty Cycle Drive ... 276
LCD Sleep Entry/Exit When SLPEN = 1 or
CS1:CS0 = 00 .................................................. 277
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 253
Master SSP I²C Bus Data ........................................ 381
Master SSP I²C Bus Start/Stop Bits ........................ 381
PWM Output ............................................................ 153
Repeat Start Condition ............................................. 186
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 372
Send Break Character Sequence ............................ 211
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 57
SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode, CKE = 0) ........................... 164
SPI Mode (Slave Mode, CKE = 1) ........................... 164
Synchronous Reception
(Master Mode, SREN) ............................. 214, 228
Synchronous Transmission .............................. 212, 226
Synchronous Transmission
(Through TXEN) ...................................... 213, 227
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 57
Time-out Sequence on Power-up
MCLR Not Tied to VDD, Case 1 ......................... 56
MCLR Not Tied to VDD, Case 2 ......................... 56
MCLR Tied to VDD, VDD Rise < TPWRT ............. 56
Timer0 and Timer1 External Clock .......................... 373
Transition for Entry to PRI_IDLE Mode ..................... 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 289
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 44
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 43
Transition to RC_RUN Mode ..................................... 44
Type-A in 1/2 MUX, 1/2 Bias Drive .......................... 266
Type-A in 1/2 MUX, 1/3 Bias Drive .......................... 268
Type-A in 1/3 MUX, 1/2 Bias Drive .......................... 270
Type-A in 1/3 MUX, 1/3 Bias Drive .......................... 272
Type-A in 1/4 MUX, 1/3 Bias Drive .......................... 274
Type-A/Type-B in Static Drive ................................. 265
Type-B in 1/2 MUX, 1/2 Bias Drive .......................... 267
Type-B in 1/2 MUX, 1/3 Bias Drive .......................... 269
Type-B in 1/3 MUX, 1/2 Bias Drive .......................... 271
Type-B in 1/3 MUX, 1/3 Bias Drive .......................... 273
Type-B in 1/4 MUX, 1/3 Bias Drive .......................... 275
USART Synchronous Receive (Master/Slave) ........ 383
USART Synchronous Transmission
(Master/Slave) ................................................. 383
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 385
AC Characteristics - Internal RC Accuracy .............. 370
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 374
CLKO and I/O Requirements ................................... 371
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 375
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 376
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 377
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 378
External Clock Requirements .................................. 369
I²C Bus Data Requirements (Slave Mode) .............. 380
I²C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 379
Master SSP I²C Bus Data Requirements ................ 382
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 381
PLL Clock ................................................................ 370
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 372
Timer0 and Timer1 External
Clock Requirements ........................................ 373
USART Synchronous Receive
Requirements .................................................. 383
USART Synchronous Transmission
Requirements .................................................. 383
© 2007 Microchip Technology Inc.
DS39629C-page 407