PIC24FJ256GB108-I Datasheet, PDF (73/352 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
TABLE 6-1: RESET FLAG BIT OPERATION
Flag Bit
Setting Event
TRAPR (RCON<15>)
IOPUWR (RCON<14>)
Trap Conflict Event
Illegal Opcode or Uninitialized W Register Access
CM (RCON<9>)
Configuration Mismatch Reset
EXTR (RCON<7>)
MCLR Reset
SWR (RCON<6>)
RESET Instruction
WDTO (RCON<4>)
WDT Time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP Instruction
IDLE (RCON<2>)
PWRSAV #IDLE Instruction
BOR (RCON<1>)
POR, BOR
POR (RCON<0>)
POR
Note: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR
POR
POR
POR
POR
PWRSAV Instruction, POR
POR
POR
—
—
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 8.0 “Oscillator Configuration” for
further details.
TABLE 6-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(CW2<10:8>)
COSC Control bits
(OSCCON<14:12>)
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
 2009 Microchip Technology Inc.
DS39897C-page 73