PIC24FJ256GB108-I Datasheet, PDF (176/352 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
FIGURE 14-2:
OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE)
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCxCON1
OCxCON2
OCxR
Rollover/Reset
OCxR buffer
OC Clock
Sources
Trigger and
Sync Sources
Clock
Select
Increment
Reset
Trigger and ^{Match Event}
Sync Logic
Comparator
OCxTMR
Match
Event
Rollover
Comparator
OCxRS buffer
Match
Event
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT0
OCFLT0
OC Output and
Fault Logic
OCx Pin
OCFA/OCFB
Reset
Rollover/Reset
OCxRS
OCx Interrupt
Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral
Pin Select” for more information.
14.3.1 PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 14-1.
EQUATION 14-1: CALCULATING THE PWM
PERIOD⁽¹⁾
PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)
where: PWM Frequency = 1/[PWM Period]
Note 1: Based on TCY = TOSC * 2, Doze mode
and PLL are disabled.
Note:
A PRy value of N will produce a PWM
period of N + 1 time base count cycles. For
example, a value of 7 written into the PRy
register will yield a period consisting of
8 time base cycles.
14.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
OCxRS and OCxR registers. The OCxRS and OCxR
registers can be written to at any time, but the duty
cycle value is not latched until a match between PRy
and TMRy occurs (i.e., the period is complete). This
provides a double buffer for the PWM duty cycle and is
essential for glitchless PWM operation.
Some important boundary parameters of the PWM duty
cycle include:
• If OCxR, OCxRS, and PRy are all loaded with
0000h, the OCx pin will remain low (0% duty
cycle).
• ·If OCxRS is greater than PRy, the pin will remain
high (100% duty cycle).
See Example 14-1 for PWM mode timing details.
Table 14-1 and Table 14-2 show example PWM
frequencies and resolutions for a device operating at
4 MIPS and 10 MIPS, respectively.
DS39897C-page 176
 2009 Microchip Technology Inc.