PIC24FJ256GB108-I Datasheet, PDF (50/352 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

TABLE 4-10: UART REGISTER MAPS
File Name Addr Bit 15
Bit 14
Bit 13 Bit 12 Bit 11
Bit 10
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
U3MODE
U3STA
U3TXREG
U3RXREG
U3BRG
U4MODE
U4STA
U4TXREG
U4RXREG
U4BRG
Legend:
0220 UARTEN
—
USIDL IREN RTSMD
—
0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
0224
—
—
—
—
—
—
0226
—
—
—
—
—
—
0228
0230 UARTEN
—
USIDL IREN RTSMD
—
0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
0234
—
—
—
—
—
—
0236
—
—
—
—
—
—
0238
0250 UARTEN
—
USIDL IREN RTSMD
—
0252 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
0254
—
—
—
—
—
—
0256
—
—
—
—
—
—
0258
02B0 UARTEN
—
USIDL IREN RTSMD
—
02B2 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN
02B4
—
—
—
—
—
—
02B6
—
—
—
—
—
—
02B8
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
UEN1 UEN0 WAKE LPBACK
UTXBF TRMT URXISEL1 URXISEL0
—
—
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK
UTXBF TRMT URXISEL1 URXISEL0
—
—
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK
UTXBF TRMT URXISEL1 URXISEL0
—
—
Baud Rate Generator Prescaler Register
UEN1 UEN0 WAKE LPBACK
UTXBF TRMT URXISEL1 URXISEL0
—
—
Baud Rate Generator Prescaler Register
ABAUD RXINV BRGH
ADDEN RIDLE PERR
Transmit Register
Receive Register
ABAUD RXINV BRGH
ADDEN RIDLE PERR
Transmit Register
Receive Register
ABAUD RXINV BRGH
ADDEN RIDLE PERR
Transmit Register
Receive Register
ABAUD RXINV BRGH
ADDEN RIDLE PERR
Transmit Register
Receive Register
Bit 2
PDSEL1
FERR
PDSEL1
FERR
PDSEL1
FERR
PDSEL1
FERR
Bit 1
PDSEL0
OERR
PDSEL0
OERR
PDSEL0
OERR
PDSEL0
OERR
Bit 0
STSEL
URXDA
STSEL
URXDA
STSEL
URXDA
STSEL
URXDA
All
Resets
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
0000
0110
xxxx
0000
0000
TABLE 4-11: SPI REGISTER MAPS
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
SPI3STAT
SPI3CON1
SPI3CON2
SPI3BUF
Legend:
0240 SPIEN
—
SPISIDL
—
— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV
0242
—
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN
CKP
0244 FRMEN SPIFSD SPIFPOL —
—
—
—
—
—
—
0248
Transmit and Receive Buffer
0260 SPIEN
—
SPISIDL
—
— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV
0262
—
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN
CKP
0264 FRMEN SPIFSD SPIFPOL —
—
—
—
—
—
—
0268
Transmit and Receive Buffer
0280 SPIEN
—
SPISIDL
—
— SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV
0282
—
—
—
DISSCK DISSDO MODE16 SMP
CKE
SSEN
CKP
0284 FRMEN SPIFSD SPIFPOL —
—
—
—
—
—
—
0288
Transmit and Receive Buffer
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SRXMPT
MSTEN
—
SRXMPT
MSTEN
—
SRXMPT
MSTEN
—
SISEL2
SPRE2
—
SISEL2
SPRE2
—
SISEL2
SPRE2
—
Bit 3
SISEL1
SPRE1
—
SISEL1
SPRE1
—
SISEL1
SPRE1
—
Bit 2
SISEL0
SPRE0
—
SISEL0
SPRE0
—
SISEL0
SPRE0
—
Bit 1
SPITBF
PPRE1
SPIFE
SPITBF
PPRE1
SPIFE
SPITBF
PPRE1
SPIFE
Bit 0
All
Resets
SPIRBF
PPRE0
SPIBEN
SPIRBF
PPRE0
SPIBEN
SPIRBF
PPRE0
SPIBEN
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000