PIC24FJ256GB108-I Datasheet, PDF (178/352 Pages) Microchip Technology – 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG)

PIC24FJ256GB110 FAMILY
REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
—
bit 15
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
OCSIDL OCTSEL2 OCTSEL1 OCTSEL0
—
U-0
—
bit 8
R/W-0
U-0
ENFLT0
—
bit 7
U-0
R/W-0, HCS R/W-0
R/W-0
R/W-0
R/W-0
—
OCFLT0 TRIGMODE OCM2⁽¹⁾
OCM1⁽¹⁾
OCM0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HCS = Hardware Clearable/Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12-10
bit 9-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare x in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
OCTSEL<2:0>: Output Compare x Timer Select bits
111 = System Clock
110 = Reserved
101 = Reserved
100 = Timer1
011 = Timer5
010 = Timer4
001 = Timer3
000 = Timer2
Unimplemented: Read as ‘0’
ENFLT0: Fault 0 Input Enable bit
1 = Fault 0 input is enabled
0 = Fault 0 input is disabled
Unimplemented: Read as ‘0’
OCFLT0: PWM Fault Condition Status bit
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
OCM<2:0>: Output Compare x Mode Select bits⁽¹⁾
111 = Center-aligned PWM mode on OCx⁽²⁾
110 = Edge-aligned PWM Mode on OCx⁽²⁾
101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state
continuously on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin
010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low
001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high
000 = Output compare channel is disabled
Note 1:
2:
The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select”.
OCFA pin controls the OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and
OCxRS are double-buffered only in PWM modes.
DS39897C-page 178
 2009 Microchip Technology Inc.