PIC16LF1904 Datasheet, PDF (63/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

6.3 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
• Default system oscillator determined by FOSC
bits in Configuration Word 1
• Secondary oscillator 32 kHz crystal
• Internal Oscillator Block (INTOSC)
6.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<1:0> bits in the Configuration Word 1.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 6-1.
6.3.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<1:0> bits in the Configuration
Word 1, or from the internal clock source. The OST
does not reflect the status of the secondary oscillator.
PIC16LF1904/6/7
6.3.3 SECONDARY OSCILLATOR
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSI and T1CKI/T1OSO
device pins.
The secondary oscillator is enabled using the
T1OSCEN control bit in the T1CON register. See
Section 17.0 “Timer1 Module with Gate Control” for
more information about the Timer1 peripheral.
6.3.4
SECONDARY OSCILLATOR READY
(T1OSCR) BIT
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (T1OSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
T1OSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
 2011 Microchip Technology Inc.
Preliminary
DS41569A-page 63