PIC16LF1904 Datasheet, PDF (31/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16LF1904/6/7
TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch PORTA
00Dh PORTB
00Eh PORTC
00Fh PORTD⁽³⁾
010h PORTE
011h PIR1
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
—
—
RE3
TMR1GIF ADIF
RCIF
TXIF
—
RE2⁽²⁾
—
RE1⁽²⁾
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RE0⁽²⁾
TMR1IF
xxxx xxxx uuuu uuuu
---- xxxx ---- uuuu
0000 ---0 0000 ---0
012h PIR2
013h —
—
—
—
—
—
LCDIF
—
— ---0 -0-- ---0 -0--
Unimplemented
—
—
014h —
Unimplemented
—
—
015h TMR0
016h TMR1L
017h TMR1H
018h T1CON
019h T1GCON
Timer0 Module Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
—
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS1
DONE
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1ON 0000 00-0 uuuu uu-u
T1GSS0 0000 0x00 uuuu uxuu
01Ah
to —
01Fh
Unimplemented
—
—
Bank 1
08Ch TRISA
08Dh TRISB
08Eh TRISC
08Fh TRISD⁽³⁾
090h TRISE
091h PIE1
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
—
—
—
TMR1GIE ADIE
RCIE
—
TXIE
—⁽²⁾
—
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
TRISE2⁽³⁾
—
TRISE1⁽³⁾
—
1111 1111 1111 1111
TRISE0⁽³⁾ ---- 1111 ---- 1111
TMR1IE 0000 ---0 0000 ---0
092h PIE2
093h —
—
—
—
—
—
LCDIE
—
— ---- -0-- ---- -0--
Unimplemented
—
—
094h —
Unimplemented
—
—
095h OPTION_REG
096h PCON
097h WDTCON
098h —
WPUEN INTEDG
STKOVF STKUNF
—
—
Unimplemented
T0CS
—
WDTPS4
T0SE
RWDT
WDTPS3
PSA
RMCLR
WDTPS2
PS2
RI
WDTPS1
PS1
POR
WDTPS0
PS0 1111 1111 1111 1111
BOR 00-1 11qq qq-q qquu
SWDTEN --01 0110 --01 0110
—
—
099h OSCCON
09Ah OSCSTAT
09Bh ADRESL
09Ch ADRESH
09Dh ADCON0
09Eh ADCON1
09Fh —
—
IRCF3
IRCF2
T1OSCR
—
OSTS
A/D Result Register Low
A/D Result Register High
—
CHS4
CHS3
ADFM ADCS2 ADCS1
Unimplemented
IRCF1
HFIOFR
CHS2
ADCS0
IRCF0
—
CHS1
—
—
—
CHS0
—
SCS1
LFIOFR
SCS0 -011 1-00 -011 1-00
HFIOFS 0-q0 --00 q-qq --0q
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
GO/DONE ADON -000 0000 -000 0000
ADPREF1 ADPREF0 0000 ---- 0000 ----
—
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
Unimplemented, read as ‘1’.
PIC16LF1904/7 only.
 2011 Microchip Technology Inc.
Preliminary
DS41569A-page 31