PIC16LF1904 Datasheet, PDF (28/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP (CONTINUED)
400h
40Bh
40Ch
46Fh
470h
47Fh
BANK 8
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
480h
48Bh
48Ch
4EFh
4F0h
4FFh
BANK 9
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
500h
50Bh
50Ch
56Fh
570h
57Fh
BANK 10
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
580h
58Bh
58Ch
5EFh
5F0h
5FFh
BANK 11
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
600h
60Bh
60Ch
66Fh
670h
67Fh
BANK 12
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
680h
68Bh
68Ch
6EFh
6F0h
6FFh
BANK 13
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
700h
70Bh
70Ch
76Fh
770h
77Fh
BANK 14
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
800h
80Bh
80Ch
86Fh
870h
87Fh
BANK 16
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
880h
88Bh
88Ch
8EFh
8F0h
8FFh
BANK 17
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
900h
90Bh
90Ch
96Fh
970h
97Fh
BANK 18
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
980h
98Bh
98Ch
9EFh
9F0h
9FFh
BANK 19
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A00h
A0Bh
A0Ch
A6Fh
A70h
A7Fh
BANK 20
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
A80h
A8Bh
A8Ch
AEFh
AF0h
AFFh
BANK 21
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B00h
B0Bh
B0Ch
B6Fh
B70h
B7Fh
BANK 22
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
B80h
B8Bh
B8Ch
BEFh
BF0h
BFFh
BANK 23
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
C00h
C0Bh
C0Ch
C6Fh
C70h
C7Fh
BANK 24
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
C80h
C8Bh
C8Ch
CEFh
CF0h
CFFh
BANK 25
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D00h
D0Bh
D0Ch
D6Fh
D70h
D7Fh
BANK 26
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
D80h
D8Bh
D8Ch
DEFh
DF0h
DFFh
BANK 27
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E00h
E0Bh
E0Ch
E6Fh
E70h
E7Fh
BANK 28
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
E80h
E8Bh
E8Ch
EEFh
EF0h
EFFh
BANK 29
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
F00h
F0Bh
F0Ch
F6Fh
F70h
F7Fh
BANK 30
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Common RAM
(Accesses
70h – 7Fh)
Legend:
= Unimplemented data memory locations, read as ‘0’