PIC16LF1904 Datasheet, PDF (163/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16LF1904/6/7
FIGURE 18-5:
RX/DT pin
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RX/DT input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE⁽¹⁾ TXIE⁽¹⁾
—
—
—
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF⁽¹⁾ TXIF⁽¹⁾
—
—
—
TMR1IF
RCREG
EUSART Receive Register
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
SPBRGL
EUSART Baud Rate Generator, Low Byte
SPBRGH
EUSART Baud Rate Generator, High Byte
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
Legend:
*
Note 1:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
Page provides register information.
PIC16LF1904/7 only.
Register
on Page
166
166
93
94
98
160*
165
167*
167*
134
164
 2011 Microchip Technology Inc.
Preliminary
DS41569A-page 163