PIC16LF1904 Datasheet, PDF (141/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16LF1904/6/7
REGISTER 16-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
bit 7
R/W-1/1
INTEDG
R/W-1/1
TMR0CS
R/W-1/1
TMR0SE
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate
000
1:2
001
1:4
010
1:8
011
1 : 16
100
1 : 32
101
1 : 64
110
1 : 128
111
1 : 256
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA
PS<2:0>
TMR0
Timer0 Module Register
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Register
on Page
72
141
139*
103
 2011 Microchip Technology Inc.
Preliminary
DS41569A-page 141