PIC16LF1904 Datasheet, PDF (180/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16LF1904/6/7
FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
TX/CK pin
(SCKP = 0)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ^{‘0’}
‘0’
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
166
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
166
INTCON
PIE1
PIR1
GIE
PEIE TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
93
TMR1GIE ADIE
RCIE⁽¹⁾ TXIE⁽¹⁾
—
—
—
TMR1IE
94
TMR1GIF ADIF
RCIF⁽¹⁾ TXIF⁽¹⁾
—
—
—
TMR1IF
98
RCREG
EUSART Receive Register
160*
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
165
SPBRGL
EUSART Baud Rate Generator, Low Byte
167*
SPBRGH
EUSART Baud Rate Generator, High Byte
167*
TXSTA
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
TX9D
164
Legend:
*
Note 1:
— = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.
Page provides register information.
PIC16LF1904/7 only.
DS41569A-page 180
Preliminary
 2011 Microchip Technology Inc.