PIC16LF1904 Datasheet, PDF (183/288 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

PIC16LF1904/6/7
18.4.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 18.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
18.4.2.4 Synchronous Slave Reception
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Set the RX/DT and TX/CK TRIS controls to ‘1’.
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUD1CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
166
BAUD2CON ABDOVF RCIDL
—
SCKP BRG16
—
WUE
ABDEN
166
INTCON
GIE
PEIE
TMR0IE INTE
IOCIE TMR0IF
INTF
IOCIF
93
PIE1
TMR1GIE ADIE
RCIE
TXIE
—
—
—
TMR1IE
94
PIR1
TMR1GIF
ADIF
RCIF
TXIF
—
—
—
TMR1IF
98
RCREG
EUSART Receive Register
160*
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
165
SPBRGL
EUSART Baud Rate Generator, Low Byte
167*
SPBRGH
EUSART Baud Rate Generator, High Byte
167*
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH
TRMT
TX9D
164
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.
* Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41569A-page 183