PIC24F16KA102_11 Datasheet, PDF (60/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
7.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 7-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
TABLE 7-2:
Reset Type
POR
BOR
MCLR
WDTO
SWR
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
FNOSC Configuration bits
(FNOSC<10:8>)
COSC Control bits
(OSCCON<14:12>)
7.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the system Reset
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
Reset Type
Clock Source
SYSRST Delay
System Clock
Delay
Notes
POR⁽⁶⁾
EC
TPOR + TPWRT
—
1, 2
FRC, FRCDIV
TPOR + TPWRT
TFRC
1, 2, 3
LPRC
TPOR + TPWRT
TLPRC
1, 2, 3
ECPLL
TPOR + TPWRT
TLOCK
1, 2, 4
FRCPLL
TPOR + TPWRT
TFRC + TLOCK 1, 2, 3, 4
XT, HS, SOSC
TPOR+ TPWRT
TOST
1, 2, 5
XTPLL, HSPLL
TPOR + TPWRT
TOST + TLOCK 1, 2, 4, 5
BOR
EC
TPWRT
—
2
FRC, FRCDIV
TPWRT
TFRC
2, 3
LPRC
TPWRT
TLPRC
2, 3
ECPLL
TPWRT
TLOCK
2, 4
FRCPLL
TPWRT
TFRC + TLOCK 2, 3, 4
XT, HS, SOSC
TPWRT
TOST
2, 5
XTPLL, HSPLL
TPWRT
TFRC + TLOCK 2, 3, 4
All Others
Any Clock
—
—
None
Note 1: TPOR = Power-on Reset (POR) delay.
2: TPWRT = 64 ms nominal if the Power-up Timer (PWRT) is enabled; otherwise, it is zero.
3: TFRC and TLPRC = RC oscillator start-up times.
4: TLOCK = PLL lock time.
5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the
oscillator clock to the system.
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC,
and in such cases, FRC start-up time is valid.
Note: For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”.
DS39927C-page 60
 2008-2011 Microchip Technology Inc.