PIC24F16KA102_11 Datasheet, PDF (141/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
17.3 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator (BRG) reload
value, use Equation 17-1.
EQUATION 17-1: COMPUTING BAUD RATE
RELOAD VALUE⁽¹⁾
FSCL = -------------------------------F---^C---^Y--------------------------------
I2C1BRG + 1 + _{1----0---}---0-F--0-^C--0-^Y--_---0---0---0-
or
I2C1BRG
=


--F---^C---^Y---
FSCL
–
1----0---^{---0-F--0-C--0-Y--}^{---0---0---0-}
–1
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
17.4 Slave Address Masking
The I2C1MSK register (Register 17-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2C1MSK register causes the slave
module to respond whether the corresponding address
bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set
to ‘00100000’, the slave module will detect both
addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
Note:
As a result of changes in the I²C protocol,
the addresses in Table 17-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
TABLE 17-1: I²C™ CLOCK RATES⁽¹⁾
Required
System
FSCL
I2C1BRG Value
FCY
(Decimal)
(Hexadecimal)
100 kHz
16 MHz
157
9D
100 kHz
8 MHz
78
4E
100 kHz
4 MHz
39
27
400 kHz
16 MHz
37
25
400 kHz
8 MHz
18
12
400 kHz
4 MHz
9
9
400 kHz
2 MHz
4
4
1 MHz
16 MHz
13
D
1 MHz
8 MHz
6
6
1 MHz
4 MHz
3
3
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled;
Actual
FSCL
100 kHz
100 kHz
99 kHz
404 kHz
404 kHz
385 kHz
385 kHz
1.026 MHz
1.026 MHz
0.909 MHz
TABLE 17-2: I²C™ RESERVED ADDRESSES⁽¹⁾
Slave
R/W
Address Bit
Description
0000 000
0 General Call Address⁽²⁾
0000 000
1 Start Byte
0000 001
x Cbus Address
0000 010
x Reserved
0000 011
x Reserved
0000 1xx
x HS Mode Master Code
1111 1xx
x Reserved
1111 0xx
x 10-Bit Slave Upper Byte⁽³⁾
Note 1: The address bits listed here will never cause an address match, independent of the address mask settings.
2: The address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
 2008-2011 Microchip Technology Inc.
DS39927C-page 141