PIC24F16KA102_11 Datasheet, PDF (133/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
To set up the SPI module for the Enhanced Buffer
Master (EBM) mode of operation:
1. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register.
2. Write the desired settings to the SPI1CON1
and SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 1.
3. Clear the SPIROV bit (SPI1STAT<6>).
4. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
5. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
6. Write the data to be transmitted to the SPI1BUF
register. Transmission (and reception) will start
as soon as data is written to the SPI1BUF
register.
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1. Clear the SPI1BUF register.
2. If using interrupts:
a) Clear the respective SPI1IF bit in the IFS0
register.
b) Set the respective SPI1IE bit in the IEC0
register.
c) Write the respective SPI1IPx bits in the
IPC2 register to set the interrupt priority.
3. Write the desired settings to the SPI1CON1 and
SPI1CON2 registers with the MSTEN bit
(SPI1CON1<5>) = 0.
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SS1 pin.
6. Clear the SPIROV bit (SPI1STAT<6>).
7. Select Enhanced Buffer mode by setting the
SPIBEN bit (SPI1CON2<0>).
8. Enable SPI operation by setting the SPIEN bit
(SPI1STAT<15>).
FIGURE 16-2:
SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)
SCK1
SS1/FSYNC1
Sync
Control
SDO1
Control
Clock
Select
Edge
Shift Control
SDI1
bit 0
SPI1SR
1:1 to 1:8
1:1/4/16/64
Secondary
Primary
FCY
Prescaler
Prescaler
SPI1CON1<1:0>
SPI1CON1<4:2>
Enable
Master Clock
Transfer
Transfer
8-Level FIFO 8-Level FIFO
Receive Buffer Transmit Buffer
Read SPI1BUF
SPI1BUF
Write SPI1BUF
16
Internal Data Bus
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DS39927C-page 133