PIC24F16KA102_11 Datasheet, PDF (40/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

TABLE 4-20: CLOCK CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
RCON
0740 TRAPR IOPUWR SBOREN —
—
DPSLP
—
PMSLP EXTR
OSCCON
0742
—
COSC2 COSC1 COSC0
—
NOSC2 NOSC1 NOSC0 CLKLOCK
CLKDIV
0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0
—
OSCTUN
0748
—
—
—
—
—
—
—
—
—
REFOCON 074E ROEN
—
ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
—
HLVDCON 0756 HLVDEN —
HLSIDL
—
—
—
—
—
VDIR
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
SWR
—
—
—
—
BGVST
SWDTEN
LOCK
—
TUN5
—
IRVST
WDTO
—
—
TUN4
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SLEEP
CF
—
TUN3
—
HLVDL3
IDLE
BOR
POR (Note 1)
— SOSCEN OSWEN (Note 2)
—
TUN2
—
TUN1
—
TUN0
3140
0000
—
—
—
0000
HLVDL2 HLVDL1 HLVDL0 0000
TABLE 4-21: DEEP SLEEP REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
DSCON
0758 DSEN
—
—
—
—
—
DSWAKE 075A
—
—
—
—
—
—
DSGPR0 075C
DSGPR1 075E
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The Deep Sleep registers are only reset on a VDD POR event.
Bit 9
Bit 8
Bit 7
Bit 6
—
—
—
—
—
DSINT0 DSFLT
—
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
Bit 5
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets⁽¹⁾
—
—
—
DSBOR RELEASE 0000
DSWDT DSRTCC DSMCLR —
DSPOR 0000
0000
0000
TABLE 4-22: NVM REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13
Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
NVMCON 0760 WR WREN WRERR PGMONLY —
—
—
—
—
ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000⁽¹⁾
NVMKEY 0766 —
—
—
—
—
—
—
— NVMKEY7 NVMKEY6 NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-23: PMD REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
PMD1
PMD2
PMD3
PMD4
Legend:
0770 —
— T3MD T2MD T1MD —
—
0772 —
—
—
—
—
—
—
0774 —
—
—
—
— CMPMD RTCCMD
0776 —
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
IC1MD
—
—
I2C1MD
—
CRCPMD
—
Bit 6
U2MD
—
—
—
Bit 5
U1MD
—
—
—
Bit 4
—
—
—
EEMD
Bit 3
Bit 2
SPI1MD
—
—
REFOMD
—
—
—
CTMUMD
Bit 1
—
—
—
HLVDMD
Bit 0 All Resets
ADC1MD
OC1MD
—
—
0000
0000
0000
0000