|
PIC24F16KA102_11 Datasheet, PDF (137/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology | |||
|
◁ |
PIC24F16KA102 FAMILY
REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED)
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to â0â for the Framed
SPI modes (FRMEN = 1).
REGISTER 16-3: SPI1CON2: SPI1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
SPIFPOL
â
â
â
â
â
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
â
â
â
â
â
â
SPIFE
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-2
bit 1
bit 0
FRMEN: Framed SPI1 Support bit
1 = Framed SPI1 support is enabled
0 = Framed SPI1 support is disabled
SPIFSD: Frame Sync Pulse Direction Control on SS1 Pin bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
Unimplemented: Read as â0â
SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced Buffer is enabled
0 = Enhanced Buffer is disabled (Legacy mode)
ï£ 2008-2011 Microchip Technology Inc.
DS39927C-page 137
|
▷ |