PIC24F16KA102_11 Datasheet, PDF (31/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
4.2 Data Address Space
The PIC24F core has a separate, 16-bit wide data
memory space, addressable as a single linear range.
The data space is accessed using two Address
Generation Units (AGUs), one each for read and write
operations. The data space memory map is displayed
in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This gives a data space address range of 64 Kbytes or
32K words. The lower half of the data memory space
(that is, when EA<15> = 0) is used for implemented
memory addresses, while the upper half (EA<15> = 1) is
reserved for the Program Space Visibility (PSV) area
(see Section 4.3.3 “Reading Data From Program
Memory Using Program Space Visibility”).
PIC24F16KA102 family devices implement a total of
768 words of data memory. Should an EA point to a
location outside of this area, an all zero word or byte will
be returned.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in
byte-addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all the
data space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
FIGURE 4-3:
DATA SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES
Implemented
Data RAM
MSB
Address
0001h
07FFh
0801h
0DFFh
1FFF
MSB
LSB
SFR Space
Data RAM
LSB
Address
0000h
07FEh
0800h
SFR
Space
Near
Data Space
0DFEh
1FFEh
7FFFh
8001h
Unimplemented
Read as ‘0’
7FFFh
8000h
Program Space
Visibility Area
FFFFh
Note: Data memory areas are not shown to scale.
FFFEh
 2008-2011 Microchip Technology Inc.
DS39927C-page 31