PIC24F16KA102_11 Datasheet, PDF (106/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER⁽¹⁾
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
R/W-0, HS
DSINT0
bit 8
R/W-0, HS
U-0
DSFLT
—
bit 7
U-0
R/W-0, HS R/W-0, HS R/W-0, HS
U-0
R/W-0, HS
—
DSWDT
DSRTCC DSMCLR
—
DSPOR^(2,3)
bit 0
Legend:
R = Readable bit
-n = Value at POR
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
DSRTCC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
Unimplemented: Read as ‘0’
DSPOR: Power-on Reset Event bit^(2,3)
1 = The VDD supply POR circuit was active and a POR event was detected
0 = The VDD supply POR circuit was not active, or was active but did not detect a POR event
Note 1:
2:
3:
All register bits are cleared when the DSCON<DSEN> bit is set.
All register bits are reset only in the case of a POR event outside Deep Sleep mode, except bit, DSPOR,
which does not reset on a POR event that is caused due to a Deep Sleep exit.
Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
DS39927C-page 106
 2008-2011 Microchip Technology Inc.